Analog Modeling,Verification and characterization Senior Lead Engineer

Job Description

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim. Create Liberty (.lib) timing and power models and validate them against transistor-level designs. Develop and maintain self-checking testbenches and test plans for model verification. Conduct functional analysis and verification of modeled IPs using simulators like VCS. Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices. Automate model generation and verification workflows using Tcl, Perl, or Skill scripting. Interface with design and verification teams to ensure model accuracy and completeness. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field and 3+ years of relevant hardware modeling experience OR Master's degree and 2+ years of experience OR PhD and 1+ year of experience. Required Skills & Experience: 5+ years of experience with timing/power characterization and view generation tools (e.g., Silicon Smart, HSPICE, FineSim). Strong understanding of mixed-signal analog IP design and functionality. Expertise in Verilog and Verilog-AMS behavioral modeling. Hands-on experience with simulation and verification tools such as VCS. Experience with Liberty file format and creating timing/power views. Knowledge of AMS verification environments is a plus. Strong scripting skills in Tcl, Perl, and/or Skill for automation. Excellent problem-solving, collaboration, and communication skills.