Job Description

Custom Layout Engineer Experience: 5 to 8 Years Education: BE or MTech in Electronics / VLSI Engineering Role & Responsibilities: Design and develop critical analog and custom digital layout blocks Perform layout verification such as LVS, DRC, Antenna checks, quality checks, and documentation Ensure on-time delivery of high-quality block-level layouts Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project milestones Guide and review sub-block layouts developed by junior team members Contribute to project management activities Communicate effectively with global engineering teams to ensure successful project execution Required Skills & Qualifications: 58 years of experience in analog/custom layout design in advanced CMOS nodes Proficient in Cadence VLE/VXL and Mentor Graphics Calibre (DRC/LVS) Hands-on experience in laying out critical analog blocks such as: Temperature Sensors, PLLs, ADCs/DACs, LDOs, Bandgap References, Reference Generators, Charge Pumps, Current Mirrors, Comparators, Differential Amplifiers Strong understanding of analog layout fundamentals: Matching, Electro-migration, Latch-up, Coupling/Crosstalk, IR-drop, Active/passive parasitic effects Ability to account for layout effects on speed, capacitance, power, and area Excellent problem-solving skills in physical verification of custom layouts Multiple tape-out experience is a strong plus Excellent verbal and written communication skills Preferred (Nice to Have): Strong understanding of memory design methodology Experience with various memory layout levels including: Custom memory bits, Leaf cells, Control blocks, Read/write components, Sense amplifiers, Decoders