Design Verification Engineer ll Bangalore ll Immediate Joiner Only

Job Description

Role & responsibilities Extensive experience in executing IP verification or subsystem verification of complex blocks. Proficiency in System Verilog (SV), Universal Verification Methodology (UVM), assertions, test benches, test plans, and coverage. Strong experience in verifying Fabric/NOC/Interconnect blocks. Knowledge of protocols such as AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management. Preferred candidate profile Design Verification Engineer Perks and benefits