Job Description

JD: Verification Engineer 8 years experience Job Overview Duties include As a Verification engineer, should have the hands-on experience related to block level, sub-system level and chip top level verification. Development and working with object-oriented verification languages (System Verilog, UVM) Have background in Mixed Signal devices. Able to handle multiple blocks (good at time management). Good at debugging design and environment related issues. Should work closely with the designers to understand the design changes and implement the same in Verification. Should be good with scripting languages. Essential Functions Should be good at Digital basics. Develop environment and tests for block level verification and extend the same to block and chip top level verification. Good understanding of RAL, Code coverage and functional coverage and implementing the same Scripting using Perl, Python and Shell Simulations using gate level netlist at various PVT corners. Generation of vcd files for power analysis. Ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced work environment. Process : If the resume is shortlisted, the candidate should come to the Aura office for the F2F discussion ( 3 rounds of discussion on the same day) If shortlisted he should be ready to start immediately We are in 5 days WFO mode & no Hybrid mode