DFT Design Lead Engineer

7 - 12 years

30.0 - 45.0 Lacs P.A.

Bengaluru, Noida

Posted:2 months ago| Platform: Naukri logo

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Skills Required

JTAGScan InsertionScanningDFTAtpgBoundary ScanMbist

Work Mode

Work from Office

Job Type

Full Time

Job Description

Mirafra Technologies Hiring DFT Lead Engineers: Experience - 7 to 12 years Notice Period - 0 to 90 days (45 days or lesser notice period will be preferred 1st) Location - Bangalore Please find the Job Description Below: Minimum 7+ years of relevant work experience in DFT. Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level. Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys . Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent Expertise in coverage improvement techniques Experience in - Stuck at, Transition, Deley faults, Bridging fault, IDDQ ATPG simulation - with SDF - should possess good debug skills Scripting experience - TCL/Shell/Perl/Python Tester/ATE Pattern debug. if Interested, please share your updated resume at sayantikamajumdar@mirafra.com Thanks and Regards, Sayantika Majumdar Senior Talent Acquisition Specialist Mirafra Technologies Email - sayantikamajumdar@mirafra.com Call- +91 - 9007115796

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