Job Description

BE / BTech / ME / MTech in ECE with 4+ years of relevant experience in ASIC PD. Expertise in digital physical design Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk Hands on experience of working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs Experience in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization Experience in making ECOs both Metal and logic level ecos Experience DRC and LVS cleanup of designs during sign off Exposure to lower node technologies 16nm or below preferred