Job Description

Good understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification, understand the usage of tools like Virtuoso, Finesim, Hspice, Xcellium, Simvision, Waveview. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing is a plus. Hands on experience in building SPICE testbenches at Block, Full chip Level. Hand on experience in building the COSIM/ Mixed signal verification environment is a plus. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using Perl, Python is a plus. Previous work experience in memory related fields is a plus. Must possess good communication, debugging skills and ability to work well in a team.