Job Description:We are looking for a Junior Test Engineer to join our dynamic semiconductor testing team in Bangalore. If you are passionate about working in the semiconductor industry and possess the ability to support test lab operations, we want to hear from you! You will play an integral role in performing data collection, compiling reports, and ensuring quality test execution.Roles & Responsibilities:Collect data in Automated Test Equipment (ATE) environment (93K).Generate reports based on collected data and collaborate with Test Engineers.Be part of a team providing 24x7 support for the test lab.Conduct precise measurements using bench equipment such as oscilloscopes, pattern generators, and power supplies.Handle semiconductor package samples while following ESD precautions.Skills Required:0-2 years of experience in the semiconductor or electronics testing domain.Basic hands-on experience with ATE, particularly 93K.Familiarity with MS Excel, Perl, and Python for data management.Knowledge of bench equipment like oscilloscopes, pattern generators, and power supplies.Understanding of semiconductors, CMOS, and package sample handling.Awareness of ESD protocols and precautions.Educational Qualification:B.E. in Electronics or Diploma in Electronics.

Key Responsibilities:Physical Verification closure for Arm CPU implementation.Multiple tape-outs completed with a strong focus on Physical Verification closure.Deep understanding of DRC/LVS/PERC/Antenna/DFM and associated concepts for advanced nodes on TSMC and Samsung foundries.Experience with running Physical Verification on Arm CPU designs for advanced technology nodes.Expertise in fixing issues related to DRC/LVS/PERC/Antenna/DFM on base/metal layers and recommending appropriate fixes for P&R tool flow.Strong knowledge of advanced technology nodes like Samsung Foundry (4nm/3nm) is a significant advantage.

Job Description:Memory design engineer.Responsibilities:As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.Required Skills and Experience :We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree.You have some understanding of computer architecture and concepts.We expect you to have basic understanding of CMOS Transistors, their behaviors.We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits.Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.You have an engineering demeanor and Passion for Circuit design.Expected to have good interpersonal skills.Minimum 5Yrs of experience in SRAM / memory design Margin, Char and its related quality checks.Nice To Have Skills and Experience :You know basic scripting languages, e.g. Perl/TCL/Python.Some Experience of working on Cadence or Synopsys flows.Experience with Circuit Simulation and Optimization of standard cells.

Key Responsibilities:Lead the Report to Record (R2R) process and ensure compliance with IFRS and US GAAP standards.Oversee month-end close activities, reconciliations, and detailed financial reporting.Collaborate with cross-functional teams to optimize finance processes using SAP S4 Hana.Drive process improvements and challenge existing methods to boost efficiency and streamline operations.Prepare accurate financial statements and reports, ensuring data integrity and alignment with accounting policies.Qualifications:Experience: 3-5 years of hands-on R2R experience, ideally within a multinational environment.Education: A Masters degree in Finance from a reputed institution is preferred.Preferred Systems: Proficiency in SAP S4 Hana.Strong working knowledge of IFRS and US GAAP standards.Advanced Excel skills (pivot tables, complex formulas, etc.).Strong analytical and problem-solving skills, with a focus on continuous improvement.Excellent organizational skills with the ability to manage multiple priorities simultaneously.

Are you a Physical Design Engineer looking to make a significant impact in the semiconductor industry? Join our team and be a part of cutting-edge ASIC Implementation and chip design! Key Responsibilities:Drive ASIC Implementation, from Synthesis to Place & Route.Manage DFT, Timing Closure, and Power Optimization.Perform DRC/LVS/PERC/ERC analysis for Physical Verification.Collaborate with international teams to optimize IP and push boundaries in Physical Design. Required Skills:3+ years of experience in ASIC Implementation and Timing Closure.Expertise in Synthesis, DFT, Floorplan, Place & Route.Proficiency in scripting languages: Tcl, Perl, Python, Make.Strong communication and problem-solving skills. Bonus Skills:Experience with low-power design techniques.Knowledge of ARM-based SoCs.Hands-on experience with Verilog RTL design.

We are seeking a skilled Full Stack Developer to join our dynamic team in Bangalore. This role is perfect for someone passionate about building scalable dashboards and developing innovative full-stack solutions for large-scale web applications.Responsibilities:Design and develop efficient, scalable dashboards and extractors for various applications.Integrate complex methodologies and tools using innovative software design.Lead the development process, including requirement gathering, specification, development, testing, and documentation.Education:Bachelor's or Master's degree in Computer Science, Information Science, Electronics, or a related field.Experience:Minimum 3+ years of experience as a Full Stack Developer in large-scale web development.Technical Skills:Proficient in SvelteKit.Experience with REST APIs (added advantage).Familiarity with Asynchronous client-rendered web pages.Soft Skills:Strong communication and collaboration abilities.Eager to explore new technologies and self-driven problem-solving.Willing to share knowledge and work as part of a team.Domain Knowledge (Optional but Preferred):Experience with Dashboards and Databases.

RequirementsGood knowledge of Standard cell layout designGood knowledge of CMOS logicExperience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable.Expertise in using industry-standard tools like cadence Virtuoso, Calibre Experience in implementation of ESD layouts, handling Antenna/EM, etcAbility to independently debug layout issuesGood team playerGood in SKILL programming or other scripting languages

Job Description:The Architecture and Technology Group (ATG) at Arm is looking for an Architecture Verification Engineer to contribute to the development of Architecture Compliance Kits that ensure Arm implementations adhere to architectural specifications. This is an exciting opportunity to work on cutting-edge Arm architectures and apply hardware/software verification skills to develop high-quality Architecture Verification IP.Key Responsibilities:Analyze architecture definitions, conduct feasibility studies, and develop verification strategies.Design and develop test cases/scenarios using Assembly, C, HVL, and automation techniques.Collaborate with internal teams to ensure compliance with Arms architectural specifications.Develop and execute test plans and verification methodologies.Contribute to the success of the team by taking on additional responsibilities.Required Skills & Experience:1-2 years of experience in engineering (CPU/IP verification is a plus).Strong understanding of computer architecture.Proficiency in C/C++/Assembly programming with good software engineering practices.Experience with test plan and testcase development in a verification environment.Familiarity with Unix/Linux environments.Prior experience in CPU verification is an added advantage.Why Join Us?Work on cutting-edge Arm architectures and System IPs.Be part of a highly skilled and innovative verification team.Excellent career growth opportunities in a world-class semiconductor company.