Job Description

PREFERRED EXPERIENCE: • Minimum of 4-6 years' experience • Worked with EDA tools that enable RTL quality checks • Experience with analyzing the STA timing reports and identifying both the design and constraints related issues. • Ability to multitask, ramp up quickly on new flows/tools/ideas. • Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable Notice Period - 0 to 45 Days REQUIREMENTS: Attention to the detail Very good communication skills (both written and verbal) Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions) Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets Summarize the regression results periodically to track the progress. Able to debug the basic issues like SDC loading errors, check timing (no clock, unconstrained, no_clock, QoR violations)