Embedded Firmware Developer Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis (http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a talented embedded firmware developers to join our dynamic team The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products This is what you are responsible for Design, implement, and test firmware for embedded systems used in AI chips Optimize firmware for performance and power consumption to meet stringent AI application requirements Work closely with hardware engineers to ensure seamless integration of firmware with hardware components Diagnose and resolve firmware issues, ensuring robustness and reliability of the embedded systems Collaborate with cross-functional teams including software developers, hardware engineers, and QA testers to deliver high-quality products Create and maintain comprehensive documentation for firmware designs, implementations, and debugging procedures Necessary Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field Minimum of 3 years of experience in embedded firmware development Proficiency in programming languages such as C and C++ Experience with embedded systems and microcontroller programming Familiarity with real-time operating systems (RTOS) and embedded Linux Knowledge of hardware interfaces and communication protocols (e g , I2C, SPI, UART, CAN) Experience with debugging tools and techniques, such as JTAG, oscilloscopes, and logic analyzers Preferred Qualifications Experience in developing firmware for AI or machine learning applications Familiarity with AI chip architectures and performance optimization techniques Knowledge of version control systems, such as Git Experience with scripting languages like Python for test automation and data analysis Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!

Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis (http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a highly skilled and experienced Hardware Architect to join our dynamic team The ideal candidate will have a strong background in hardware architecture, particularly in writing architectural models and conducting performance and power analysis of chips In addition to collaborating closely with our hardware team, the successful candidate will also work with our software department, which focuses on compilers, runtime software, and kernel software, to ensure cohesive and efficient chip design and functionality This is what you are responsible for Architecture Modeling Develop architecture models for AI chips Collaborate with cross-functional teams to ensure models accurately reflect design specifications and requirements Utilize industry-standard tools and methodologies for architecture modeling Performance Analysis Conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs Use simulation and analytical methods to predict and enhance chip performance Work with software teams to validate performance models with real-world applications and workloads Power Analysis Perform detailed power analysis to ensure AI chips meet stringent power consumption targets Necessary Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field Minimum of 8 years of experience in hardware architecture/design of silicon chips Strong understanding of computer architecture principles and AI chip design Proficiency in C/C++/Verilog Preferred Qualifications Excellent analytical and problem-solving skills Strong communication and teamwork abilities Ability to work in a fast-paced, collaborative environment Detail-oriented with a focus on delivering high-quality results Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!

Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a talented Implementation Engineer to join our dynamic team The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products This is what you are responsible for Synthesis and STA (static timing analysis) Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL Professional experience with ECO implementation, both functional and timing closure Experience with multi-clock, multi-power domain designs and multi-mode timing constraints Familiarity with DFT insertion Familiarity with simulation, debugging tools, and working closely with Design teams Ability to collaborate with different functional teams like RTL Design, DFT and Physical design Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure Necessary Qualifications Bachelors or Masters degree in Electronics, Computer Science Engineering, or a related field Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA Experience with Cadence, Synopsys and Mentor tools Experience with Verilog and VHDL Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP) Formal verification for RTL 2 gates and gates2gates Conformal ECO for doing complex functional ECOs Low power synthesis on smaller blocks and subsystems using DC/Genus Physical Aware synthesis Writing Timing Constraints sub-blocks and Top level Flow Automation and Scripting using TCL and Python or Perl Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!

Junior ASIC Verification Engineer Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis (http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a talented junior ASIC Verification Engineer to join our dynamic team The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products This is what you are responsible for Develop and maintain verification plans, testbenches, and test cases for ASIC designs Design and implement SystemVerilog/UVM-based verification environments Create and execute test cases to verify functionality, performance, and compliance with specifications Write testplans, testcases at unit or SOC level Necessary Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field expertise in SystemVerilog, C, C++ languages Experience with verification tools such as VCS, QuestaSim, or similar is helpful Excellent problem-solving and debugging skills Strong communication and teamwork abilities Preferred Qualifications Experience with scripting languages such as Python or Perl Programming languages such as C,C++ Knowledge of industry standards and protocols (e g , AXI, AHB, etc) Familiarity with formal verification techniques Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!