As an STA (Static Timing Analysis) Engineer at Nsemi, you ll play a crucial role in ensuring our digital designs meet timing requirements and performance standards. You will be responsible for performing timing analysis, identifying critical paths, and optimizing designs for timing closure. Your expertise in STA tools and methodologies will be essential in delivering high-quality, reliable semiconductor solutions. Join us to contribute to cutting-edge projects and advance your career in a dynamic and innovative environment. Qualification Required: Typically requires minimum of 3+ years of experience. Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Timing Constraint Generation: Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. STA Setup: Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Timing Analysis: Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Clock Domain Crossing (CDC) Analysis: Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Multicycle Paths (MCP) and False Paths: Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Timing Closure: Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Clock Tree Synthesis (CTS): Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Post-Layout STA: Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Timing Margins: Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Report Generation: Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Cross-Functional Collaboration: Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Methodology Development: Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.

As a Physical Design Engineer at Nsemi, you ll play a crucial role in transforming RTL designs into efficient, high-performance physical layouts. You ll work on floorplanning, placement, routing, and timing closure, using industry-leading EDA tools. Your expertise will ensure that our designs meet stringent performance, power, and area goals, contributing to the successful tape-out of complex semiconductor chips. This is an exciting opportunity to work on cutting-edge technology in a collaborative and innovative environment. Qualification Required: Typically requires minimum of 3+ years of experience in Physical Design with mainstream P&R tools Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment. Expertise in solving customer s problems for critical designs to achieve desired performance, area, and power targets. Responsible to develop flow and methodology for doing placement, CTS, and routing. Provide training and technical support to customers Required Technical And Professional Expertise: Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage. Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results. Experience on Floorplan design, including placement of hard macros, padring, power grid and custom analog routes. Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements). Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing). Hands-on experience with FinFET technologies is an advantage

As an RTL Design Engineer at Nsemi, you will play a pivotal role in developing high-performance digital circuits through Register Transfer Level (RTL) design. Your responsibilities will include designing, modeling, and verifying RTL code using VHDL or Verilog to create efficient and reliable digital systems. You will collaborate with cross-functional teams to ensure that your designs meet stringent performance, power, and area specifications. This role requires a strong understanding of digital logic, excellent problem-solving skills, and a commitment to quality and innovation. Qualification Required: Typically requires minimum of 3+ years of experience in System Verilog, UVM. Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches. If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality. You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews. Required Technical And Professional Expertise: Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. Understanding of verification tools like Simulator, Synthesis etc. Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. Excellent written and verbal interpersonal skills Self-motivated and great teammate

We are seeking a skilled Analog Layout Engineer to join our team at Nsemi. In this role, you ll be responsible for designing and optimizing analog and mixed-signal IC layouts, ensuring high performance and reliability. Your expertise will involve layout creation, verification, and adherence to design rules and specifications. Ideal candidates will have strong experience with analog circuit design, proficient use of layout tools, and a keen eye for detail. Join us to work on cutting-edge projects and contribute to the advancement of semiconductor technology. Qualification Required: Typically requires minimum of 3+ years of experience in Analog Circuit Design Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Expert in Power Management including hands-on DC-DC Converter, other precision analog circuits like operational amplifiers, Band-gap references, POR, Current Limit circuits, LDO regulators, comparators, oscillators etc. Experience in transceiver design for high speed interface such as Serdes, highspeed,DDR, HBM, PCIe, USB3, JESD204, Experience in transceiver design for high speed interface such as PLL,CTLE, DFE, CDR,PCIe, USB3, JESD204 Candidate should have taken atleast one block from circuit design and should be guide layout engineers for closure. Strong competency in small signal analysis and various frequency compensation techniques. Understanding of chip level ESD/LU requirements. Top-level integration, Block-level verification across PVT, Statistical Mismatch & mixed signal Verification. Hands-on working with Tools - Virtuoso/Tanner for schematic/model design & verification. Work closely with the Layout engineer to get optimized IP layout. This involves managing IP planning. Experience with Silicon validation and debug process. Planning, managing full-chip execution with team. Advantage if candidate has experience with high-current designs and/or multi-phase operation switching regulators

As an ASIC Design Verification Engineer at Nsemi, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge ASIC designs. You will utilize advanced verification methodologies, including UVM and SystemVerilog, to develop comprehensive test plans, create and execute testbenches, and identify and resolve potential issues. Your work will be pivotal in validating complex designs and ensuring they meet the highest standards of performance and quality. If you have a passion for functional verification and a keen eye for detail, this role offers an exciting opportunity to contribute to groundbreaking semiconductor projects. Qualification Required: Typically requires minimum of 3+ years of experience in System Verilog, UVM. Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches. If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality. You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews. Required Technical And Professional Expertise: Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. Understanding of verification tools like Simulator, Synthesis etc. Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. Excellent written and verbal interpersonal skills Self-motivated and great teammate