Position OverviewThis role focuses on developing and verifying Verilog RTL for protocol conversionspecifically converting from common protocols like AHB/AXI/APB to a proprietary protocol (UPI). It also includes FPGA mapping, synthesis, timing analysis, place and route, and overall system-level validation using Xilinx FPGA platforms.ResponsibilitiesVerilog RTL Development & Verification:Develop RTL for protocol conversion (AHB/AXI/APB to UPI).Design and verify both serial and parallel interfaces to meet company specifications.FPGA Mapping & Validation:Perform synthesis, mapping, timing analysis, and place & route (PnR) on Xilinx series 4 or 5 FPGAs.Generate and program the FPGA bitstream.System-Level Verification:Run system-level tests to validate FPGA transactions and address any functional, timing, or related issues.Additional (Plus):Utilize knowledge of Quad SPI Flash memory protocols and programming as needed.RequirementsAt least 5 plus years of experience.Solid experience in Verilog RTL design and verification.Proven skills in FPGA mapping and validation using Xilinx FPGAs.Familiarity with protocol conversion techniques and interface design.Understanding of memory protocols (e.g., Quad SPI Flash) is an advantage.Location preferably in Phoenix area or Silicon Valley or India – Ahmedabad/Bangalore/Pune or Europe