The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. We are seeking an experienced ASIC Verification Manager/Lead to lead the verification efforts for ARM multi core advanced CPUs based designs. The ideal candidate will have a strong background in RTL verification methodologies, UVM, C and SystemVerilog, along with proven leadership skills in managing and technically guiding verification teams. You will be responsible for driving pre-silicon verification, collaborating with cross-functional teams, and ensuring the successful validation of high-performance SoCs. Why Join Us Opportunity to work on cutting-edge ARM-based SoC designs. Lead a team in a high-impact, fast-paced environment. Competitive compensation and career growth opportunities. Work alongside some of the best minds in the semiconductor industry. What Youll Do Lead and manage the ASIC verification team to ensure high-quality verification of ARM Advance CPU based SoC designs. Define and implement verification strategies, test plans, and methodologies, release flows for complex IP and SoC design. Develop and maintain UVM-based and C-based testbenches, including constrained random testing, functional coverage, and assertions. Drive pre-silicon verification and support emulation, and FPGA prototyping. Collaborate closely with design, architecture, software, and post-silicon validation teams to ensure comprehensive verification coverage. Analyze and debug simulation failures, regressions, and coverage gaps to ensure complete verification closure. Drive automated verification infrastructure to improve efficiency and reliability. Mentor and guide junior engineers, fostering a culture of innovation and technical excellence. Track project milestones, verification progress, and report status to stakeholders. What Youll Need Bachelor s/Master s degree in Electrical Engineering, Computer Engineering, or a related field. 15+ years of experience in ASIC/SoC verification, with at least 3+ years in a managerial and leadership role. Expertise in ARM architecture, AMBA protocols (AXI, AHB, APB), and memory subsystems, PCIe, D2D Technologies. Strong hands-on experience with UVM, SystemVerilog, and functional verification methodologies. Experience with Excelium, VCS, Questa, or other industry-standard simulators. Familiarity with Formal Verification, Gate level Simulations, Static Timing Analysis, and UPF based Power-aware Verification. Hands-on experience in C/C++, Python, or Perl scripting for automation. Experience with Emulation, FPGA prototyping, and hardware-software co-verification is a plus. Excellent leadership, communication, and problem-solving skills. Preferred Qualifications: Experience in high-performance computing (HPC) or data center SoC verification. Knowledge of Arm architecture, Security verification, and Cache coherency protocols. Familiarity with post-silicon validation and bring-up processes. Prior experience working in tapeout-focused environments. We have a flexible work environment to support and help employees thrive in personal and professional capacities. As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What you will do: Participate in on-going NetSuite implementation efforts by leading detailed review of configuration and customizations, driving walkthrough and UAT activities related to finance modules of Netsuite. Drive all phases of the application project lifecycle, including requirements gathering, design, development, testing, deployment, and post-go-live support Support the implementation of new financial systems as needed (e.g. account reconciliation tool, internal controls management tool, financial reporting tool etc.) Provide ongoing technical support and system maintenance (including training, user requests for custom searches, building reports etc,) of the financial systems Analyze business processes and identify opportunities for process improvement and automation or solutions that align with Netsuite best practices. Perform system testing, including functional, integration, and regression testing, to ensure the quality and accuracy of solutions. Assist in data migration activities, including data extraction, transformation, and loading into applications. Drive business process improvements with a focus on automation Own the chart of accounts and cost center / departments structure and hierarchy maintenance Design internal controls related to finance systems and ensure operating effectiveness Provide end-user training and support, including preparing training materials, conducting training sessions, and addressing user questions and issues Effectively manage numerous projects at a given time in a fast-paced environment, balancing execution of critical deliverables across the team What you will need: Extensive (10+ years) experience managing Netsuite projects - deep understanding of and ability to develop, build and customize the platform Expertise in aligning NetSuite to key business processes (e.g. Procure to Pay, Record to Report, etc.) requirements Strong project management experience including the ability to simultaneously manage several projects Commitment to meet deadlines and ability to effectively manage competing work priorities Ability to communicate effectively and to make effective and persuasive presentations on technical or complex matters to all levels Experience working in a fast-paced environment ideally within a rapid growth company. Bachelors degree in information systems or related field required. Advanced degree a plus. Chartered Accountant / CPA / CMA or similar professional accounting qualification a strong plus. Proficient in the use of Microsoft Office Suite with strong Excel skills. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Job Description What Youll Do Deliver standards-compliant IP blocks for use in CXL / PCIE FPGAs or ASICs. Lead ASIC or FPGA projects Streamline ASIC development process with advancing tools/scripting. Achieve project management. Architect, develop and document the design using Verilog. Architect, develop and document the verification environment using System Verilog and UVM. Develop individual test-cases against the RTL. Issue and track bug reports from inception to closure. Plan staffing levels and work with HR to hire and top talent. Provide oversight and direction to employees following our procedures. Develop staff, including overseeing new employee onboarding and provide career development planning and opportunities. Empower employees to manage their jobs and goals. Delegate responsibility and expect accountability and regular feedback. Foster a spirit of teamwork and unity among department members that allows for disagreement over ideas, conflict and expeditious conflict resolution, and the appreciation of diversity and cohesiveness, supportiveness, and working together to enable each employee and the department to succeed. You will be reporting to the Director of the Design Team. What Youll Need MSEE with 8 years of experience or BSEE with 9 years of experience in ASIC or FPGA development and will report to Director -VLSI. Standard Protocol knowledge - CXL and PCIE. Solid experience with VHDL, Verilog and System Verilog. Experience with FPGA compilation tools Experience in System Verilog and UVM Excellent ability to use Randomized and Directed Verification Methodologies Experience with Unix/Linux Shell scripting Experience with source code revisioning systems, SVN, CVS, RCS e.g. Itd Be Amazing If You Had Experience in CXL / PCIE Experience in OTN / Ethernet transport systems Experience with Debugging Tools Experience with TCL, Python and C/C++ programming About You Achieve consistency Take personal pride in high standard of outputs Mentoring skills We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll Do Will be responsible for verification of IP, Block, or Subsystem at Soc Level Generate appropriate documentation for verification Responsible for analyzing/debugging given blocks/tasks in verification Should be able to develop and own the verification environment, verification components developed You will report to Lead Engineer What Youll Need: 5+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification Have worked on IP level or Block level or SoC level functional verification Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology philosophy Expert in System Verilog, Verilog, and OVM/UVM verification methodology Have working experience on AMBA interface protocols (AXI, AHB, APB) Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must Hands-on experience on working one or more of the following protocols is a must - UART, I2C, SPI, QSPI, I3C, eMMC, CAN, Hands-on experience working with one or more of the following protocols is desired - PCIe, USB, DDR, LPDDR, GBE, SATA Experience with Perl, Python or similar scripting languages will be helpful Ability to adapt learn, quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. The Senior Compensation and Benefits Analyst will be responsible for supporting various compensation and benefits program implementation across countries in Asia. This role is required to have in-depth hands-on experience in working on strategizing compensation and benefits practices aligning with local and company requirements. What Youll do: Conduct regular market benchmarking and salary surveys to ensure compensation structures are and aligned with regional trends and regulations. Lead and manage cross-functional projects related to compensation, benefits across global teams. Develop, review, and update compensation policies and benefits programs, ensuring compliance with local laws and regulations in the assigned regions. Provide data-driven insights and reports on compensation and benefit metrics, pay equity, and benefit utilization to senior leadership. Use analytics to drive decision-making and recommendations for improvement. Act as the subject matter expert (SME) in compensation and benefits for internal stakeholders, delivering regarding compensation policies, benefits programs, and salary reviews. Build a consultative and collaborative relationship with HR Business Partners, Talent Acquisition, and business leaders to provide comprehensive support and counsel on all compensation related activities, such as strategic new hire offers, promotions, international transfers, budget allocation, top talent, and retention Ensure adherence to local labor laws and regulations, managing any changes or updates to compensation or benefits plans in each region. Work closely with HR, finance, legal, and other cross-functional teams to ensure alignment and successful implementation of compensation programs. Continuously assess and recommend process improvements within the compensation and benefits function to enhance efficiency, accuracy, and employee satisfaction, while supporting and driving consistency and alignment of programs globally, to reflect the overal companys rewards philosophy. What Youll Need: 8 to10 years experience in compensation and benefits functions in the technology industry with a strong focus on international compensation, essentially, India, China, Taiwan and Korea. Added knowledge of Europe and Israel will be an advantage. Understanding of principles of all components of comepnsation and benefits, including base pay, variable pay, long term incentives and benefits administration Advanced proficiency in excel with ability to analyze data and identify trends and make recommendations Experience with Workday Advanced Compensation module will be an added benefit Ability to multitask and on multiple projects ensuring deliverables are achieved within define timelines. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Actively Lead, plan and execute SOC EMIR analysis. Collaborate with the PnR, Packaging and DFT teams in driving EMIR analysis for the SOC to converge and meet the goals of the design. Analyse and provide recommendations for layout and design changes to enhance power distribution, minimize IR drop and to mitigate EM issues in PDN and signal nets. Actively influence analysis workflows, methodologies, and tools to enhance efficiency and accuracy in delivering results. Mentor Juniors in the Team and oversee execution of EM and IR drop analysis of sub-systems. Role will involve collaboration with Verification teams and get the right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are needed. What Youll Need: Experience of 8 - 14 years. Good understanding of EM and IR fundamentals Should have solid experience in conducting detailed EMIR analysis of the PDN at Chip Top and block level Usage of industry-standard tools and methodologies to perform and analyse power and EM. Rich hands-on experience with RedhawkSC and/or Voltus Experience in EMIR simulations with package and interposer models is a big plus Must be a strong Team player Scripting and automation experience is a must. Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Open-Silicon, Inc. is looking for Senior Engineer I - DFT to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll Do Requirements Gathering: Collaborate with HR to understand their business needs and requirements for HR functional areas. Configuration and Customization: Configure Workday modules according to client specifications, including Core HCM, Absence, Advanced Analytics, Compensation, Learning, and Talent Management. Develop custom reports and calculated fields. Testing: Conduct testing of Workday configurations and customizations to ensure accuracy and functionality. Training: Provide training to end-users and client stakeholders on Workday functionality, best practices, and system updates. Support and Maintenance: Provide ongoing support and maintenance for Workday applications, troubleshoot issues, and collaborate with technical teams for problem resolution. Documentation: Create detailed technical and functional documentation for configurations and customizations. Stay Current: Stay updated with Workday updates, releases, and best practices to provide proactive recommendations. What Youll Need 5+ Years of HRIS configuration experience with in-depth knowledge of Workday configuration. Functional experience working around implementing and supporting HCM, Recruitment and Advanced Compensation functional areas in Workday. Good understanding of Workday business processes, security and report writing. Experience with large global organization and able to implement solutions under tight timelines and prioritize work effectively. Demonstrated experience handling highly sensitive and confidential information with discretion and professionalism within data privacy standards. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll need: Good understanding of overall design Flow RTL to GDS. Must have 7- 10 years of experience on signing off the full chip synthesis/STA for tape outs Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs. Deep Understanding of DFT Constraints. Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools. good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well. Good knowledge on Timing Budgets. Knowledge on Perl / TCL / Python scripting language Experience on multi voltage designs using CPF/UPF. Good understanding on timing/area/power/complexity tradeoffs on complex interface design Hands on experience on power analysis using PTPX Good understanding of VHDL / Verilog Constructs. Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus A, enthusiastic team player who enjoys working with others Experience troubleshooting issues with users Experience communicating updates and resolutions to customers and other partners complex technical concepts to other design peers in verbal and written form What Youll Do: We are looking for experienced STA engineer to lead the timing convergence of the SoCs. Responsibilities include STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence. Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts. Support Verification team to enable GLS. Guide the CTS strategies and provide feedback to Implementation Team. Manage the timing ECO generation and strategize the implementation methodology. Develop Automation scripts with-in STA tools for Methodology development. You will be reporting to Director - ASIC engineering. We have a flexible work environment to support and help employees thrive in personal and professional capacities As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll do: Actively Lead, plan and execute SOC EMIR analysis. Collaborate with the PnR, Packaging and DFT teams in driving EMIR analysis for the SOC to converge and meet the goals of the design. Analyse and provide recommendations for layout and design changes to enhance power distribution, minimize IR drop and to mitigate EM issues in PDN and signal nets. Actively influence analysis workflows, methodologies, and tools to enhance efficiency and accuracy in delivering results. Mentor Juniors in the Team and oversee execution of EM and IR drop analysis of sub-systems. Role will involve collaboration with Verification teams and get the right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are needed. What Youll Need: Experience of 3- 7 years. Good understanding of EM and IR fundamentals Should have solid experience in conducting detailed EMIR analysis of the PDN at Chip Top and block level Usage of industry-standard tools and methodologies to perform and analyse power and EM. Rich hands-on experience with RedhawkSC and/or Voltus Experience in EMIR simulations with package and interposer models is a big plus Must be a strong Team player Scripting and automation experience is a must. We have a flexible work environment to support and help employees thrive in personal and professional capacities As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What youll do: Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs. Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification. Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control. Write static timing constraints, create waivers, and devise flows for bullet proof timing checks Hiring, training and leading DFT engineers in daily tasks and activities to fulfill company road map. You will report to head of Central DFT Team. Mentor DFT engineers through out the project life cycle. What youll need: Engineer with proven technical and people management skills Collaborative team player, and out of the box mindset Good understanding in Verilog/VHDL and System Verilog Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python. Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs) Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs. Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences. Experience in scripting/reviewing SCAN/MBIST timing constraints. Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions. Good to have: Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science 10+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles. Vast experience to various DFT EDA tools from Tessent, SNPS and Cadence Experience in core wrapping, pattern retargeting & packetizing ATPG techniques. SSN knowledge. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll do : Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs. Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification. Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control. Write static timing constraints, create waivers, and devise flows for bullet proof timing checks What youll need: Engineer with proven technical and people management skills Collaborative team player, and out of the box mindset Good understanding in Verilog/VHDL and System Verilog Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python. Experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs) Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs. Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences. Experience in scripting/reviewing SCAN/MBIST timing constraints. Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions. Good to have: Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science 4-6 years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles. Experience to various DFT EDA tools from Tessent, SNPS and Cadence Experience in core wrapping, pattern retargeting packetizing ATPG techniques. SSN knowledge. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll do : Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs. Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification. Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control. Write static timing constraints, create waivers, and devise flows for bullet proof timing checks Hiring, training and leading DFT engineers in daily tasks and activities to fulfill company road map. You will report to head of Central DFT Team. Mentor DFT engineers through out the project life cycle. What youll need: Engineer with proven technical and people management skills Collaborative team player, and out of the box mindset Good understanding in Verilog/VHDL and System Verilog Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python. Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs) Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs. Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences. Experience in scripting/reviewing SCAN/MBIST timing constraints. Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions. Good to have: Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science 8-10 years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles. Vast experience to various DFT EDA tools from Tessent, SNPS and Cadence Experience in core wrapping, pattern retargeting packetizing ATPG techniques. SSN knowledge. We have a flexible work environment to support and help employees thrive in personal and professional capacities " As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll do : Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs. Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification. Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control. Write static timing constraints, create waivers, and devise flows for bullet proof timing checks Hiring, training and leading DFT engineers in daily tasks and activities to fulfill company road map. You will report to head of Central DFT Team. Mentor DFT engineers through out the project life cycle. What youll need: Engineer with proven technical and people management skills Collaborative team player, and out of the box mindset Good understanding in Verilog/VHDL and System Verilog Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python. Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs) Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs. Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences. Experience in scripting/reviewing SCAN/MBIST timing constraints. Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions. Good to have: Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science 10-15 Years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles. Vast experience to various DFT EDA tools from Tessent, SNPS and Cadence Experience in core wrapping, pattern retargeting packetizing ATPG techniques. SSN knowledge. We have a flexible work environment to support and help employees thrive in personal and professional capacities " As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.