Job Description

As a Physical Design Engineer at Nsemi, you ll play a crucial role in transforming RTL designs into efficient, high-performance physical layouts. You ll work on floorplanning, placement, routing, and timing closure, using industry-leading EDA tools. Your expertise will ensure that our designs meet stringent performance, power, and area goals, contributing to the successful tape-out of complex semiconductor chips. This is an exciting opportunity to work on cutting-edge technology in a collaborative and innovative environment. Qualification Required: Typically requires minimum of 3+ years of experience in Physical Design with mainstream P&R tools Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment. Expertise in solving customer s problems for critical designs to achieve desired performance, area, and power targets. Responsible to develop flow and methodology for doing placement, CTS, and routing. Provide training and technical support to customers Required Technical And Professional Expertise: Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage. Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results. Experience on Floorplan design, including placement of hard macros, padring, power grid and custom analog routes. Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements). Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing). Hands-on experience with FinFET technologies is an advantage