Job Description

**Verification Planning and Execution*: 2. Develop and execute comprehensive verification plans. 3. Close verification with coverage closure, ensuring high-quality results. 4. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions. 5. **Testbench Development*: 6. Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. 7. Implement reusable Verification IP (VIP) components. 8. Collaborate with third-party VIP providers. 9. Developing vertically and horizontally re-usable test-benches 10. **Methodology and Flows*: 11. Demonstrate a solid understanding of ASIC design and verification methodologies. 12. Apply object-oriented programming principles effectively. 13. Implement constraint random verification methodology. 14. **Technical Skills*: 15. Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI, SV/DPI) 16. Familiarity with industry standards (e.g., I2C/SPI/AHB). 17. Gate level simulation 18. Experience with low-power verification using UPF (Unified Power Format) is a plus. 19. Knowledge of formal verification techniques is advantageous. 20. **Collaboration and Communication*: 21. Work effectively with internal teams and external customers. 22. Strong written and verbal communication skills. 23. Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.