Job Description

As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Integration of analog blocks, Meeting RC requirements for manual/special signals 4) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip finishing) and post Tapeout eJob view release, 6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus, 7) Understanding of VLSI fabrication process, 8) Implementing timing ECOs. Implementing IR drop fixes, SPEF extraction, signal EM fixes, Noise analysis. 9) Open to new responsibilities in context of rapid technological change. 10) Good communication skills, work closely with the team members to accomplish PD milestone. 11) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing. Relevant experience of CAD tools cadence Innovus, Calibre is preferred. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.