Job Description

• 3+ years of solid experience in IP/SoC design • Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts • Good knowledge of Digital Design and RTL development • Hands-on experience with SoC Design, Verilog RTL coding • Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug • Working knowledge of Lint, CDC, PLDRC, CLP etc • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification • Manage SoC dependencies, planning and tracking of all front-end design related tasks • Working for successful design delivery for the project milestones across the design, verification and physical implementations • Should possess effective communication skills Interested candidates can share their resumes to shubhanshi@incise.in