Key Responsibilities:Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption.Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designsArchitect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores).Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques.Develop and refine RTL code in Verilog/System Verilog for ASIC development.Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design.Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power.Work on creating micro-architectural specifications and ensure the design meets project requirements.Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques.Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems.Drive the design flow from architecture and specifications through to implementation.Prepare and maintain technical documentation for designs and related processes.CDC, LINT and Integration expertise is expected.Required Skills & Experience:Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields.4-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role.Expertise in RTL design using Verilog or System Verilog.Solid understanding of digital design principles, including timing analysis, state machines, and pipelining.In-depth knowledge of ASIC design flow, from RTL to tape-out.Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence).Strong debugging and problem-solving skills.Good knowledge on scripting (Python, Perl and Shell scripting)Knowledge of power, performance, and area (PPA) optimization techniques.Experience with designing for low-power, high-speed circuits is highly desirable.Excellent communication skills and the ability to work in a team environment.Preferred Skills:Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O.Prior experience working with large, cross-functional teams and managing design schedules.Experience with software tools for RTL analysis and optimization.Hands-on experience in leading ASIC projects from specification to production.Perks and benefits According to company norms

Key Responsibilities:Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability.Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area).Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization.Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization.Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design.Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic.RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies.Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met.Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues.Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference.Qualifications:Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree.Experience:Minimum 4-14 years of experience in ASIC physical design.Proficiency in place and route (P&R), static timing analysis (STA), power analysis, and DRC/LVS checks.Experience with tools like Cadence,Innovus, Synopsys IC Compiler, or Mentor Graphics for physical design.Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus.Technical Skills:Proficiency in digital design concepts and semiconductor process flows.Strong knowledge of timing optimization techniques and power optimization strategies.Familiarity with parasitic extraction and signal integrity analysis.Ability to script in languages like Tcl, Python, or Perl to automat tasks.Preferred Skills:Experience with 3D IC design or FinFET technologies.Familiarity with full-chip tape-out procedures.Exposure to machine learning techniques in physical design optimization will be added advantage.Perks and benefits According to company norms