Job Description

Our main job is developing generators to produce final mask data from drawn base layer data and writing DRC code to verify the data. We will use the generator to build all masks for development of a new technology from initial development to product ramp. All mask data should be generated in a timely manner and error free. We work closely with NAND PI, design rule, OPC, process and tapeout team to improve the quality and efficiency of the business process by developing automation tools. Qualifications: Must have expertise in writing DRC runset ( Res, Cap, MOS, FET, etc devices) using the Calibre SVRF/TVF. Fundamental understanding of semiconductor device physics and silicon processing Understanding of design rules, and the device physics and processing issues that impacts design rules. Familiarity of layout issues associated with high density memories, electrical test structures, process monitors and alignment related structures. The ability to interface with a wide variety of people with different skill sets: design, process, process integration, OPC, layout CAD. tapeout The capability to supply innovative solutions to fix complex problems relating to generation of mask data. Solid knowledge of computer programming and software: UNIX/Linux system, Python, Perl, Shell script, C/C++,TCL. Intimate knowledge of appropriate CAD tools: Cadence df2 environments/SKILL/K2view is preferred Experience in source code management and revision control system such as tool DesignSync and Perforce Good communication and problem-solving skills are required Fluent in English and able to communicate effectively with a global team Education: A Bachelor s or Master s degree/pursuing in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering. (BS 5+ year experience or MS 3+ year experience in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering)