Job Description

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be responsible for RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires a deep understanding of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. Role & responsibilities Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality. Preferred candidate profile You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Master’s preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong understanding of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation.