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7 - 12 years
35.0 - 80.0 Lacs P.A.
Pune, Bengaluru, Hyderabad
Posted:3 months ago| Platform: 
Hybrid
Full Time
• Well versed with the Timing Closure (STA), Timing closure methodologies • Pre/Post-layout constraint development to Timing Closure • Handshake with the Design team & Develop functional/DFT constraints • Abstraction expertise like Hyperscale/ILM/ETM Required Candidate profile • RC Balancing & scaling analysis of critical data paths of full chip clock • Automation in PERL, TCL and EDA tool-specific scripting • DMSA @ full chip and custom scripts for timing fixes
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