Job Description

In this highly visible role you will be: - You will excel as you optimize designs to reach ground breaking power, area, timing goals. - Delivery of timing clean, logically equivalent netlists to physical design team. - We will empower you to collaborate with a variety of functional teams to continually question the limitations of technology. Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows