Job Description

**Job Description** We are seeking an experienced **Staff ASIC Verification Engineer*to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you. **Responsibilities:** 1. **Verification Planning and Execution*: 2. Develop and execute comprehensive verification plans. 3. Close verification with coverage closure, ensuring high-quality results. 4. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions. 5. **Testbench Development*: 6. Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. 7. Implement reusable Verification IP (VIP) components. 8. Collaborate with third-party VIP providers. 9. **Methodology and Flows*: 10. Demonstrate a solid understanding of ASIC design and verification methodologies. 11. Apply object-oriented programming principles effectively. 12. Implement constraint random verification methodology. 13. **Technical Skills*: 14. Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI). 15. Familiarity with industry standards (e.g., I2C/SPI). 16. Experience with low-power verification using UPF (Unified Power Format) is a plus. 17. Knowledge of formal verification techniques is advantageous. 18. **Collaboration and Communication*: 19. Work effectively with internal teams and external customers. 20. Strong written and verbal communication skills.