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Posted:1 week ago| Platform: 
Work from Office
Full Time
3 years Service Agreement - Freshers Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.
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